Generally, semiconductor devices are fabricated by deposited a plurality of insulating, conductive and semiconductive material layers over a substrate or workpiece, and patterning the various material layers to form integrated circuits and electronic elements thereon. Each layer is typically aligned to an underlying material layer using alignment marks. The tools used to fabricate semiconductor devices visually locate the alignment marks, the position of which are programmed into the tools.
If a material layer is transparent or translucent, as many insulating material layers and semiconductive material layers are, as well as photoresists or hard masks that are used as masks to pattern material layers, the tool can “see through” the insulating layer, semiconductor material layer or photoresist and locate the alignment marks. However, many conductive layers are optically opaque, and thus additional steps must be taken to align them.
One way to align optically opaque layers is to form recessed alignment marks in an underlying material layer, by forming them simultaneously while conductive lines or vias are formed in a damascene process, removing a portion of the material from the alignment marks, and depositing the opaque layer over the material layer with recessed alignment marks. In theory, the alignment marks would then be visible on the top surface of the opaque layer, e.g., as depressions.
However, if the recessed alignment marks are formed in a damascene formed layer, such as conductive lines or vias formed in an insulating layer, and the insulating layer is subjected to a chemical mechanical polish (CMP) process, (as is typical to remove excess conductive material from the top surface of the insulating layer to form the conductive lines or vias) the edges of the alignment marks become eroded by the CMP process, and thus the edges are not sharp. This makes it difficult to use the alignment marks to align a subsequently deposited opaque layer, because the depressions transferred to the topography of the opaque layer are not as visible on the top surface of the opaque layer. The presence of clearly defined alignment marks is required for extremely tight alignment tolerance, as dictated by device performance.
There are other problems with using a CMP process over recessed alignment marks. Debris from the CMP slurry can become trapped in the alignment marks, making the topography of a subsequently deposited layer less visible, or not visible at all, particularly if the alignment marks are shallow. In addition, the deposition of opaque layers over such alignment marks give rise to jagged edges in the depressions in the topography of the opaque layer over the alignment marks, making the depressions unusable for alignment. Furthermore, the CMP slurry materials left in the alignment marks can react with some materials used in subsequent etch processes, such as chlorine or fluorine, causing the alignment marks to explode, making them unusable as alignment marks. This creates foreign materials all over the chip, leads to delamination of layers, and thus adversely affects the device performance and reduces yield.
A recent development in semiconductor memory devices are referred to as resistive memory devices, such as magnetic random access memory (MRAM) devices. In MRAM devices, the spin of electrons, rather than the charge, is used to indicate the presence of a “1” or “0.” MRAM devices comprise conductive lines (wordlines and bitlines) positioned in a different direction, e.g., perpendicular to one another in different metal layers, the conductive lines sandwiching a resistive memory element comprising a magnetic stack or magnetic tunnel junction (MTJ), which functions as a magnetic memory cell. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces the magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a “0” or “1,” is storable in the alignment of magnetic moments. The resistance of the magnetic memory cell depends on the moment's alignment. The stored state is read from the magnetic memory cell by detecting the component's resistive state.
The MTJ's of MRAM devices typically comprise a first magnetic layer, a tunnel insulator formed over the first magnetic layer, and a second magnetic layer formed over the tunnel insulator. The first magnetic layer and the second magnetic layer each typically comprise one or more layers of magnetic materials and/or metal materials, for example. The first magnetic layer may comprise a seed layer of Ta and/or TaN, an antiferromagnetic layer such as PtMn disposed over the seed layer, and one or more magnetic material layers comprising CoFe, NiFe, CoFeB, Ru, other materials, or combinations thereof disposed over the antiferromagnetic layer, as examples. The first magnetic layer is also referred to as a fixed layer because its magnetic polarity is fixed. The second magnetic layer may comprise one or more magnetic material layers comprising CoFe, NiFe, CoFeB, other magnetic material layers, or combinations thereof, as examples. The second magnetic layer is also referred to as a free layer because its magnetic polarity changes when the magnetic memory cell is written to. The tunnel insulator may comprise a thin insulator such as Al2O3 or semiconductive materials, as examples.
Copper is often used for the material of conductive lines of MRAM devices, because of its high conductivity and low resistance. However, copper is difficult to etch, and damascene processes using CMP processes are often used to form copper lines and metallization alignment marks in conductive line and via levels. Furthermore, because the first magnetic layer and second magnetic layer of MTJ's comprise metals, they are opaque.
What is needed in the art are improved methods of aligning the opaque magnetic stacks or MTJ's of MRAM devices to underlying material layers that may be formed by CMP, such as the wordlines, bitlines, or conductive via levels of the MRAM array.